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1 i n development features ? 20ns maximum access time ? asynchronous operation, func tionally compatible with industry-standard 512k x 32 srams ? cmos compatible inputs and output levels, three-state bidirectional data bus - 3.3 volt io, 1.8 volt core ? radiation performance - total-dose: >100krad(si) - sel immune: 100mev-cm 2 /mg - seu error rate = 2.9x10 -16 errors bit/day assuming geosynchronous orbit, adam?s 90% worst environment, and 312khz default scrub rate (=99.4% sram availability) - neutron fluence: 3.0e14n/cm 2 - dose rate - upset tbd rad(si)/sec - latchup tbd rad(si)/sec ? packaging options: - 68-lead ceramic quad fl atpack (6.898 grams) ? standard microcircuit drawing tbd - qml compliant part introduction the ut8er512k32 is a high-performance cmos static ram organized as 524,288 words by 32 bits. easy memory expansion is provided by active low and high chip enables (e1 , e2), an active low output enable (g ), and three-state drivers. this device has a power-down feature that reduces power consumption by more than 90% when deselected . writing to the device is accomplishe d by driving chip enable one (e1 ) input low, chip enable two (e2) high and write enable (w ) input low. data on the 32 i/o pins (dq0 through dq31) is then written into the location specified on the address pins (a0 through a8). reading from the device is accomplished by taking chip enable one (e1 ) and output enable (g ) low while forcing write enable (w ) and chip enable two (e2) high. under these conditions, the contents of the memory location specified by the address pins will appear on the i/o pins. the 32 input/output pins (dq0 through dq31) are placed in a high impedance state when th e device is deselected (e1 high or e2 low), the outputs are disabled (g high), or during a write operation (e1 low, e2 high and w low). to reduce bit error rates caused by single event phenomenon in space, the ut8er512k32 employ s an embedded edac (error detection and correction) having code engine with auto scrubbing. when a double bit error occurs in a word, the ut8er512k32 asserts an mbe output to the host. figure 1. ut8er512k32 sram block diagram memory array 512k x 32 pre-charge circuit column select row select a3 a4 a6 a7 a8 a9 a17 a18 data control i/o circuit a10 a11 a12 a13a14 a15 dq(31) to dq(0) e1 w e2 g a2 a16 read/write circuit edac a5 a1 a0 busy , busy_warning mbe standard products ut8er512k32 monolithic 16m radhard sram advanced data sheet may, 2006
2 i n development pin names device operation the ut8er512k32 has four control inputs called enable 1 (e1 ), enable 2 (e2), write enable (w ), and output enable (g ); 19 address inputs, a(18:0); and 32 bidirectional data lines, dq(31:0). e1 and e2 device enables control device selection, active, and standby modes. asserting e1 and e2 enables the device, causes i dd to rise to its active value, and decodes the 19 address inputs to select one of 524,288 words in the memory. w controls read and write operat ions. during a read cycle, g must be asserted to enable the outputs. table 1. sram device operation truth table notes: 1. ?x? is defined as a ?don?t care? condition. 2. device active; outputs disabled. table 2. edac control pin operation truth table notes: 1. ?x? is defined as a ?don?t care? condition a(18:0) address dq(31:0) data input/output e1 enable (active low) e2 enable (active high) w write enable g output enable v dd1 power (1.8) v dd2 power (3.3v) v ss ground mbe multiple bit error busy b device status busy_warning advanced for device status 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 top view dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 v ss dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 v ss a0 a1 a2 a3 a4 a5 a17 v ss a18 w a6 a7 a8 a9 a10 v dd1 v dd1 a11 a12 a13 a14 a15 a16 e1 g e2 v dd2 v ss busy b busy w mbe v dd2 v ss dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 v ss dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 figure 2. 25ns sram pinout (68) 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 g w e2 e1 i/o mode mode xxxhdq(31:0) 3-state standby x x l x dq(31:0) 3-state standby l h h l dq(31:0) data out word read x l h l dq(31:0) data in word write h h h l dq(31:0) all 3-state 3-state mbe busy b busy_w i/o mode mode h h h read uncorrectable bit error l h h read valid data out xh h x device ready x h l x device ready / early scrub request coming xl x not accessible device busy
3 i n development read cycle a combination of w and e2 greater than v ih (min) and e1 and g less than v il (max) defines a read cycle. read access time is measured from the latt er of device enable, output enable, or valid address to valid data output. sram read cycle 1, the address access in figure 3a, is initiated by a change in address inputs while the chip is enabled with g asserted and w deasserted. valid data appears on data outputs dq(31:0) after the specified t av q v is satisfied. outputs re main active throughout the entire cycle. as long as device enable and output enable are active, the address inputs may change at a rate equal to the minimum read cycle time (t avav ). sram read cycle 2, the chip enable-controlled access in figure 3b, is initiated by the latter of either e1 and e2 going active while g remains asserted, w remains deasserted, and the addresses remain stable fo r the entire cycle. after the specified t etqv is satisfied, the 32-bit word addressed by a(18:0) is accessed and appears at the data outputs dq(31:0). sram read cycle 3, the output enable-controlled access in figure 3c, is initiated by g going active while e1 and e2 are asserted, w is deasserted, and the addresses are stable. read access time is t glqv unless t av q v or t etqv (reference figure 3b) have not been satisfied. sram edac status indications during a read cycle, if mbe is low, the data is good. if mbe is high the data is corrupted. write cycle a combination of w and e1 less than v il (max) and e2 greater than v ih (min) defines a write cycle. the state of g is a ?don?t care? for a write cycle. the outputs are placed in the high-impedance state when either g is greater than v ih (min), or when w is less than v il (max). write cycle 1, the write enable-controlled access in figure 4a, is defined by a write terminated by w going high, with e1 and e2 still active. the write pulse width is defined by t wlwh when the write is initiated by w , and by t etwh when the write is initiated by e1 and e2. unless the outputs have been previously placed in th e high-impedance state by g , the t wlqz before applying data to the 32 bidirectional pins dq(31:0) to avoid bus contention. write cycle 2, the chip enable -controlled access in figure 4b, is defined by a write terminated by the latter of e1 or e2 going inactive. the write pulse width is defined by t wlef when the write is initiated by w , and by t etef when the write is initiated by either e1 or e2 going active. for the w initiated write, unless the outputs have b een previously placed in the high-impedance state by g , the user must wait t wlqz before applying data to the thirty-two bidirectional pins dq(31:0) to avoid bus contention. memory scrubbing/cycle stealing the ut8er512k32 sram uses architectural improvements and embedded error detection and correction to maintain unsurpassed levels of seu protection. this is accomplished by what aeroflex refers to as cycle stealing. when the device asserts busy_warning followed by busy , the user must de-assert e1 or e2 within the minimum specification for an access cycle (t avav ). to minimize the sy stem design impact for reduced speed operation, th e edge relationship between busy_warning and busy is programmable via the sequence described in figure 5a. the effective error rate will be flux dependent (rate at which radiation is applied) and not simply let dependent. as a result, some users may desire an increased scrub rate to lower the error rate at the sacrifice of reduced total throughput, while others may desire a lower scrub rate to increase the total throughput and accept a higher error rate in a low flux environment. this rate at which the sram controller will correct errors from the memory is user programmable. the required sequence is described in figure 5a. data is corrected not only durin g the internal scrub, but again during a user requested read cycle. if the mbe signal is asserted once the data is valid (t avav ), if the data presented contains at least two errors an d should be considered corrupt. radiation hardness the ut8er512k32 sram inco rporates special design, layout, and process features which allows operation in a limited radiation environment. table 3. radiation hardness design specifications 1 notes: 1. the sram is immune to latchup to particles >100mev-cm 2 /mg. 2. 90% worst case particle environment, geosynchronous orbit, 100 mils of aluminum. supply sequencing no supply voltage sequencing is required between v dd1 and v dd2 . total dose 100k rad(si) heavy ion error rate 2 tbd errors/bit-day
4 i n development absolute maximum ratings 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maxi mum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limit s indicated in the operational sections of this specification is not recommended. exposure to absolu te maximum rating conditions for extended periods may af fect device reliability and performance. 2. test per mil-std-883, method 1012. recommended operating conditions symbol parameter limits v dd1 dc supply voltage -0.3 to 2.0v v dd2 dc supply voltage -0.3 to 3.8v v i/o voltage on any pin -0.3 to 3.8v t stg storage temperature -65 to +150 c p d maximum power dissipation 1.2w t j maximum junction temperature +150 c jc thermal resistance, junction-to-case 2 5 c/w i i dc input current 5 ma symbol parameter limits v dd1 positive supply voltage 1.7 to 1.9v v dd2 positive supply voltage 3.0 to 3.6v t c case temperature range (c) screening: -55 to +125 c (w) screening: -40 to +125 c v in dc input voltage 0v to v dd2
5 i n development dc electrical characteristics (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening) notes: * post-radiation perform ance guaranteed at 25 c per mil-std-883 method 1019 at 3.0e5 rad(si). 1. measured only for in itial qualification and after process or design ch anges that could affect input/output capacitance. 2. supplied as a design limit bu t not guaranteed or tested. 3. not more than one output may be shorted at a time for maximum duration of one second. 4. v ih = v dd2 (max), v il = 0v. symbol parameter condition min max unit v ih high-level input voltage .7*v dd2 v v il low-level input voltage .3*v dd2 v v ol low-level output voltage i ol = 8ma,v dd2 =v dd2 (min) .2*v dd2 v v oh high-level output voltage i oh = -4ma,v dd2 =v dd2 (min) .8*v dd2 v c in 1 input capacitance ? = 1mhz @ 0v 12 pf c io 1 bidirectional i/o capacitance ? = 1mhz @ 0v 12 pf i in input leakage current v in = v dd2 and v ss -2 2 a i oz three-state output leakage current v o = v dd2 and v ss v dd2 = v dd2 (max), g = v dd2 (max) -2 2 a i os 2, 3 short-circuit output current v dd2 = v dd2 (max), v o = v dd2 v dd2 = v dd2 (max), v o = v ss -100 +100 ma i dd1 (op 1 )v dd1 supply current operating @ 1mhz inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 25 ma i dd1 (op 2 )v dd1 supply current operating @ 50mhz, inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 200 ma i dd2 (op 1 )v dd2 supply current operating @ 1mhz inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 1ma i dd2 (op 2 )v dd2 supply current operating @ 50mhz, inputs : v il = v ss + 0.2v, v ih = v dd2 -0.2v, i out = 0 v dd1 = v dd1 (max), v dd2 = v dd2 (max) 12 ma i dd1 (sb) 4 i dd2 (sb) 4 supply current standby @ 0hz cmos inputs , i out = 0 e1 = v dd2 -0.2, e2 = gnd v dd1 = v dd1 (max), v dd2 = v dd2 (max) 25 100 ma a i dd1 (sb) 4 i dd2 (sb) 4 supply current standby a(16:0) @ 50mhz cmos inputs , i out = 0 e1 = v dd2 - 0.2, e2 = gnd, v dd1 = v dd1 (max), v dd2 = v dd2 (max) 25 100 ma a
6 i n development ac characteristics read cycle (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening, v dd1 = v dd1 (min), v dd2 = v dd2 (min)) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. guaranteed but not tested. 2. three-state is defined as a 200mv ch ange from steady-state output voltage. 3. the et (enable true) notation refe rs to the latter falling edge of e1 or rising edge of e2. 4. the ef (enable false) notation refe rs to the latter rising edge of e1 or falling edge of e2. symbol parameter ut8er512 min max unit figure t avav 1 read cycle time 20 ns 3a t avqv address to data valid from address change 20 ns 3c t axqx 2 output hold time 3 ns 3a t glqx 1,2 g -controlled output enable time 0 ns 3c t glqv g -controlled output data valid 7 ns 3c t ghqz 2 g -controlled output three-state time 7 ns 3c t etqx 2,3 e-controlled output enable time 5 ns 3b t etqv 3 e-controlled access time 20 ns 3b t efqz 4 e-controlled output three-state time 2 7ns3b t etmv e-controlled error flag time 20 ns 3b t av m v address to error flag valid 20 ns 3a t axmx address to error flag hold ti me from address change 3 ns 3a t glmv g -controlled error flag valid 7 ns 3c t glmx g -controlled error flag enable time 5 ns 3c t etmx e-controlled error fl ag enable time 5 ns 3b
7 i n development assumptions: 1. e1 and g < v il (max) and e2 and w > v ih (min) 2. busy > v oh (min) a(18:0) dq(31:0) figure 3a. sram read cycle 1: address access t avav t avqv , t avmv t axqx , t axmx previous valid data valid data valid data mbe assumptions: 1. g < v il (max) and w > v ih (min) 2. busy > v oh (min) a(18:0) figure 3b. sram read cycle 2: chip enable access latter of e1 low, and e2 high data valid t efqz t etqv , t etmv t etqx , t etmx dq(31:0) data valid mbe figure 3c. sram read cycle 3: output enable access a(18:0) mbe g t ghqz assumptions: 1. e1 < v il (max), e2 and w > v ih (min) 2. busy > v oh (min) t glqv , t glmv t glqx , t glmx t avqv data valid dq(31:0) t blqx t bhqz t blqv data valid
8 i n development ac characteristics write cycle (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening, v dd1 = v dd1 (min), v dd2 = v dd2 (min)) notes : * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. tested with g high. 2. three-state is defined as 200mv ch ange from steady-state output voltage. symbol parameter min max unit figure t avav 1 write cycle time 20 ns 4a/4b t etwh device enable to end of write 17 ns 4a t av e t address setup time for write (e1 /e2- controlled) 0 ns 4b t av w l address setup time for write (w - controlled) 0 ns 4a t wlwh write pulse width 17 ns 4a t whax address hold time for write (w - controlled) 0 ns 4a t efax address hold time for device enable (e1 /e2- controlled) 0 ns 4b t wlqz 2 w - controlled three-state time 7 ns 4a/4b t whqx 2 w - controlled output enable time 6 ns 4a t etef device enable pulse width (e1/ e2 - controlled) 17 ns 4b t dvwh data setup time 12 ns 4a t whdx data hold time 0 ns 4a t wlef device enable controlled write pulse width 17 ns 4b t dvef data setup time 12 ns 4a/4b t efdx data hold time 0 ns 4b t av w h address valid to end of write 17 ns 4a t whwl 1 write disable time 5 ns 4a
9 i n development assumptions: 1. g < v il (max). (if g > v ih (min) then q(31:0) and mbe will be in three- state for the entire cycle.) 2. busy > v oh (min) w t avwl figure 4a. sram write cycle 1: w - controlled access a(18:0) q(31:0) e1 t avav d(31:0) applied data t dvwh, t dvef t whdx t etwh, t wlef t wlwh t whax t whqx t wlqz t avwh t whwl e2 t blwh
10 i n development t efdx assumptions & notes: 1. g < v il (max). (if g > v ih (min) then q(31:0) and mbe will be in three-state for the entire cycle.) 2. either e1 / e2 scenario can occur. 3. busy > v oh (min) a(18:0) figure 4b. sram write cycle 2: enable - controlled access w e1 d(31:0) applied data e1 q(31:0) t wlqz t etef t wlef t dvef t avav t avet t avet t efax t efax or e2 e2 mbe
11 i n development symbol parameter min max unit figure t avav 1 address valid to address valid 100 ns 5a t av c l address valid to control low 100 ns 5a t av e x address valid to enable valid 200 ns 5a t wtbl 1 user programmable - warning true to busy low see table 4 5b t blex busy low to enable true 25 ns 5b t blbh busy low to busy high 50 75 ns 5b t bhev busy high to enable valid 0 ns 5b t bhwf busy high warning false 25 ns 5b ac characteristics for edac function (pre and post-radiation)* (-55 c to +125 c for (c) screening and -40 c to +125 c for (w) screening, v dd1 = v dd1 (min), v dd2 = v dd2 (min)) notes: * post-radiation performance guaranteed at 25 o c per mil-std-883 method 1019. 1. see table 4 for user programmable information. table 4: edac programming configuration table data bit parameter min max function a 0 - 3 scrub rate 1 0 15 as scrub rate changes from 0 - 15, then the interval between scrub cycles will change as follows: 0 = 20 mhz 6 = 312 khz 11 = 9.76 khz 1 = 10 mhz 7 = 156 khz 12 = 4.88 khz 2 = 5 mhz 8 = 78 khz 13 = 2.44 khz 3 = 2.5 mhz 9 = 39 khz 14 = 1.22 khz 4 = 1.25 mhz 10 = 19.5 khz 15 = .61 khz 5 = 625 khz a 4 - 7 busy warning 2 0 15 if busy warning changes from 0 - 15, then the interval t wtbl between busy and busy warning will change as follows: 0 = 0 ns 6 = 300 ns 11 = 550 ns 1 = 50 ns 7 = 350 ns 12 = 600 ns 2 = 100 ns 8 = 400 ns 13 = 650 ns 3 = 150 ns 9 = 450 ns 14 = 700 ns 4 = 200 ns 10 = 500 ns 15 = 750 ns 5 = 250 ns a 8 bypass edac bit 3 0 1 if 0, then normal edac operation will occur. if 1, then edac will be bypassed. a 9 read / write control register 0 1 if 0, then dq 0 - 8 will be written into the control register if 1, then dq 0 - 8 will be asserted on the data buss notes: 1. default scrub rate is 312 khz. 2. the default for t wtbl is 500 ns. 3.the default state for a8 is 0.
12 i n development note: 1. mbe is driven high by the user. 2. lower 8 bits of the last address are used to configure the control register. addr e1 low, and e2 high oe t avcl t avav1 mbe figure 5a. writing control register assumptions: 1. busy > v oh before the start of the conf iguration cycle. ignore busy during configuration cycle. 70000h 7ff00h 3a500h 55a00h 10500h 000xxh t avex figure 5b. scrub cycle busy busy- warn i ng e1 high or e2 low t wtbl t bhwf t bhev t blbh t blex assumptions: 1. the conditions pertain to both a read or write.
13 i n development data retention characteristics (pre and post-radiation)* (v dd2 = v dd2 (min), 1 sec dr pulse) symbol parameter minimum maximum unit v dr v dd1 for data retention 1.0 v i ddr 1 data retention current 600 600 600 12 a a a ma t efr 1,2 chip deselect to data retention time 0 ns t r 1,2 operation recovery time t avav ns v dd1 data retention mode t r 1.7v v dr > 1.0v figure 6. low v dd data retention waveform t efr e1 v dd2 v in <0.3v dd2 cmos e2 v ss v in >0.7v dd2 cmos 1.7v notes: 1. 50pf including scope probe and test socket. 2. measurement of data output o ccurs at the low to high or hi gh to low transition mid-point (i.e., cmos input = v dd2 /2). 90% input pulses 10% < 2ns < 2ns cmos 0.0v v dd2 -0.05v figure 7. ac test loads and input waveforms 1.5v 188 ohms 50pf notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019. 1. e1 = v dd2 or e2 = v ss all other inputs = v dd2 or v ss 2. v dd2 = 0 volts to v dd2 (max) -55 o c 25 o c 125 o c -40 o c
14 i n development packaging notes: 1. all exposed metallized areas are gold plated over nickel per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. lead finishes are in acco rdance with mil-prf-38535. figure 8. 68-lead c eramic quad flatpack
15 i n development ordering information 512k x 32 sram ut **** ** - * * * * * lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) screening: (c) = military temperature range flow (-55 c to +125 c) (p) = prototype flow (w) = extended industrial temperature range flow (-40 c to +125 c) package type: (w) = 68-lead ceramic quad flatpack access time: (20) = 20ns access time (68 cqfp) device type: (8er512k32) =512k x 32 sram notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when or dering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per aeroflex colorado spri ngs manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. military temperature range flow per aero flex colorado springs manufacturing flow s document. devices are tested at -55 c, notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when or dering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per aeroflex colorado spri ngs manufacturing flows document. tested at 25 c only. lead finish is gold only. radiation neither tested nor guaranteed. 4. military temperature range flow per aero flex colorado springs manufacturing flow s document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed.
16 i n development 512k x 32 sram: smd 5962 - ******* ** lead finish: (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) case outline: (x) = 68-lead ceramic quad flatpack class designator: (q) = qml class q (v) = qml class v device type (01) = 20ns access time, cmos i/o, 68-lead ceramic quad flatpack (-55 c to +125 c) (02) = 20ns access time, cmos i/o, 68-lead ceramic quad flatpack (-40 c to +125 c) drawing number: tbd total dose: (r) = 100k rad(si) (f) = 300k rad(si) federal stock class designator: no options ** * notes: 1.lead finish (a,c, or x) must be specified. 2.if an ?x? is specified when ordering, part marking will match the lead finish and will be eith er ?a? (solder) or ?c? (gold). 3.total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.
17 i n development notes
18 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties.

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